Architect Labs

Making custom silicon accessible to everyone

Architect LabsAug 27, 2026

Making custom silicon accessible to everyone

Architect Labs launch preview
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SeedCinematic500K-1MExplainerB2BGlobalGAUS

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Architect Labs is an AI research lab building a system that designs, verifies, and deploys custom silicon end-to-end from a written specification, aimed at chip companies, AI labs, neoclouds, and workload owners who want their own ASICs without running a traditional multi-year design cycle. The launch introduces Redwood, a frontier AI accelerator designed end-to-end by their AI system in under two weeks from a high-level specification written by two human architects . Rather than sequential handoffs between architecture, RTL, verification, firmware, and kernels, the system co-optimized the performance model, RTL, UVM environments, formal proofs, firmware, drivers, and compute kernels in a single loop, starting from zero pre-existing accelerator IP . The chip targets low-power physical AI, and Redwood Nano, the ultra-low-power variant, is deployed on an FPGA running live inference on multi-billion-parameter models like Llama and Qwen . Projected onto Samsung 8nm, the Jetson Orin Nano's process class, Redwood delivers 1.75x the decode throughput at 1.9x lower power, a 3.4x performance-per-watt gain against a measured Jetson baseline running the same model . The company frames this as a step toward recursive self-improvement, with the Qwen3 model running on Redwood already exposed as an API endpoint used to optimize the next generation of the chip. Architect Labs is based in Palo Alto and was founded by Ebrahim Hussain and Aaditya Subedi . Hussain started college at 15 and worked on Apple's silicon teams and on Tesla's AI5 chip for self-driving and Optimus robotics, while Subedi came from Harvard research on code verification and early-stage neocloud work, with the two meeting at Stanford to research AI for chip design . The launch matters now because it lands alongside the company's emergence from stealth with seed funding, and it puts a concrete, measurable accelerator behind a thesis that has mostly lived in research papers, that future workloads will each get their own chip if the design process itself can be automated.

Comments (15)

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P
Priya RamanAug 28, 2026

Two weeks from spec to silicon is either a tapeout miracle or a very generous definition of 'deployed'. Which one is it?

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Reem AlkhalifaAug 28, 2026

Would love to chat for a piece I'm working on. what does 'designed' mean here, RTL only or full physical implementation?

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Kwesi OtienoAug 28, 2026

ok wait, an AI designed a chip that beats NVIDIA and you buried it under a 240 character tweet? this should be a 20 minute mini doc.

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Marta BergqvistAug 28, 2026

Perf/watt claims without the workload, batch size, and quantization are basically astrology for hardware people.

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Tomoyuki H.Aug 28, 2026

The b-roll of wafers in the video is gorgeous but I counted three cuts that hid the actual thermal reading. staff engineers noticed.

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deltaflowAug 28, 2026

Beats NVIDIA at what exactly. edge inference? datacenter? a very specific matmul on tuesdays?

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Benito RossiAug 28, 2026

hot take: this is the last chip company that will ever raise a seed round without an agent in the loop from day one.

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Anselmo WuAug 28, 2026

the chip that designs itself eventually forgets who asked for it.

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Nadia FeldmanAug 28, 2026

the launch tweet is doing a lot of heavy lifting with that 'beats NVIDIA' phrasing. respect the pull, questioning the truth.

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Chae-young LimAug 28, 2026

impression to like ratio on this tweet is suspicious in a good way. either the algorithm loves you or the silicon crowd is genuinely stunned.

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Olumide KayodeAug 28, 2026

How are you actually getting these into customer hands? foundry slots, packaging, board bringup, none of that is a 2 week story.

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Hiroko TanabeAug 28, 2026

the thumbnail choice of a glowing die on a black background is such a 2019 hardware startup move and I mean that lovingly.

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Vikram SethiAug 28, 2026

we prototyped something adjacent to this internally around 2019 and the bottleneck was never the design, it was the verification runs. curious how the AI handles coverage closure.

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Zara OkonkwoAug 28, 2026

if you're hiring physical design or DV folks I have a brilliant candidate coming off a stealth silicon co. ping me.

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Finn HalvorsenAug 28, 2026

building in the compiler layer for custom accelerators and honestly rooting for you, though now I have to rewrite my pitch deck tonight.