hardware intelligence is building tools for the engineers who design and verify the silicon that runs modern AI workloads. Its first product, Wave, is a terminal-native waveform debugger with a verification agent built in, aimed at ASIC and FPGA teams who currently rely on legacy GUI viewers to sift through multi-gigabyte simulation dumps after a failed assertion. Wave can jump to the exact simulation tick where a design broke, answer questions about signal behavior in plain English, and propose candidate fixes with different trade-offs, all inside the terminal environment engineers already work in.
The launch matters because chip design has become a bottleneck for the same AI boom driving demand for custom accelerators at Google, Amazon, OpenAI, and every hyperscaler building their own silicon. Verification and debug still run on tooling patterns from the early 2000s, with per-seat licenses that can reach six figures a year. hardware intelligence positions Wave as the first step in a broader agent-native toolchain rebuilt for that industry, with early benchmark claims on ChipBench and NVIDIA's CDBP suite.
The San Francisco company is part of Y Combinator's Summer 2026 batch and was founded by Athreya Anand and Rishov Sarkar. Anand, the CEO, was previously a tech lead at Google working on agentic tooling and prediction models, with earlier stints at AWS Inferentia and Tesla, and holds a Master's in Machine Learning and AI from Georgia Tech. Sarkar holds a PhD in Electrical and Computer Engineering from Georgia Tech and has worked on simulators for AMD's AI Engine accelerator and on LLVM-based compilation flows at Siemens EDA, giving the team a direct background in the simulation and verification stack they are trying to replace.
Comments (15)
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Priya VaidyaJul 28, 2026
A terminal-native waveform viewer is the kind of thing every verification engineer has muttered about while staring at GTKWave. Curious what the agent actually does when a testbench fails at 3am.
K
Kostya M.Jul 28, 2026
The tweet buries the lede. 'AI tools for the chips your AI runs on' should have been the first line, not the parenthetical vibe.
R
Renée LacroixJul 28, 2026
Free tagline rewrite: 'Wave: debug silicon at the speed of thought.' You're welcome, keep the terminal aesthetic in the promo shots.
D
Damilola O.Jul 28, 2026
Does Wave expose a CLI-scriptable API or is the agent the only interface? Asking because our CI pipeline has opinions and none of them are polite.
H
hiroakiJul 28, 2026
Chip verification is the last honest profession in software. Glad someone is finally pointing agents at signal traces instead of writing another Notion clone.
M
Marco FerettiJul 28, 2026
What's the pricing shape here, seat-based or per-simulation-hour? EDA tools historically have margins that would make a SaaS founder weep, curious where you land.
O
Ollie BramwellJul 28, 2026
I'll evaluate this properly once I finish migrating our flow off Verilog-XL. Circle back in Q3 2027.
S
Sana AkhtarJul 28, 2026
The waveform-debugger-in-terminal demo would sing with better pacing. First 4 seconds are dead air before the trace loads, that's where retention dies.
Y
Yuki TanabeJul 28, 2026
Are you learning waveform anomaly detection from labeled bug traces, or is the agent purely LLM-orchestrated over VCD dumps? Big difference in what 'built-in' means.
C
Chetan R.Jul 28, 2026
For the underlying method question, prior work on signal-level anomaly detection uses graph representations of the netlist. Would love to know if Wave leverages RTL structure or treats traces as opaque time series.
M
Mireille P.Jul 28, 2026
We shipped something adjacent internally at a large search company circa 2019 for internal ASIC bring-up. The terminal-native angle is the actually novel bit, tooling teams always wanted this and got a web UI instead.
F
Farrah NasserJul 28, 2026
Hi, working on a piece about YC S26 hardware-adjacent startups. Would love five minutes when you have them, happy to hold anything on background.
T
Tomas LindqvistJul 28, 2026
How small was the team when Wave first booted a real waveform? Two people and a lot of coffee, or is chip tooling still a five-engineer minimum?
A
Adaobi E.Jul 28, 2026
If you're hiring verification-savvy engineers who can also stomach an agent stack, I know someone leaving a fabless shop in Austin. DMs open.
K
Kazimierz W.Jul 28, 2026
Chip designs are basically the crown jewels for most customers. Where does the trace data live when the agent processes it, and is on-prem an option from day one?
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hardware intelligence is building tools for the engineers who design and verify the silicon that runs modern AI workloads. Its first product, Wave, is a terminal-native waveform debugger with a verification agent built in, aimed at ASIC and FPGA teams who currently rely on legacy GUI viewers to sift through multi-gigabyte simulation dumps after a failed assertion. Wave can jump to the exact simulation tick where a design broke, answer questions about signal behavior in plain English, and propose candidate fixes with different trade-offs, all inside the terminal environment engineers already work in. The launch matters because chip design has become a bottleneck for the same AI boom driving demand for custom accelerators at Google, Amazon, OpenAI, and every hyperscaler building their own silicon. Verification and debug still run on tooling patterns from the early 2000s, with per-seat licenses that can reach six figures a year. hardware intelligence positions Wave as the first step in a broader agent-native toolchain rebuilt for that industry, with early benchmark claims on ChipBench and NVIDIA's CDBP suite. The San Francisco company is part of Y Combinator's Summer 2026 batch and was founded by Athreya Anand and Rishov Sarkar. Anand, the CEO, was previously a tech lead at Google working on agentic tooling and prediction models, with earlier stints at AWS Inferentia and Tesla, and holds a Master's in Machine Learning and AI from Georgia Tech. Sarkar holds a PhD in Electrical and Computer Engineering from Georgia Tech and has worked on simulators for AMD's AI Engine accelerator and on LLVM-based compilation flows at Siemens EDA, giving the team a direct background in the simulation and verification stack they are trying to replace.
Comments (15)
A terminal-native waveform viewer is the kind of thing every verification engineer has muttered about while staring at GTKWave. Curious what the agent actually does when a testbench fails at 3am.
The tweet buries the lede. 'AI tools for the chips your AI runs on' should have been the first line, not the parenthetical vibe.
Free tagline rewrite: 'Wave: debug silicon at the speed of thought.' You're welcome, keep the terminal aesthetic in the promo shots.
Does Wave expose a CLI-scriptable API or is the agent the only interface? Asking because our CI pipeline has opinions and none of them are polite.
Chip verification is the last honest profession in software. Glad someone is finally pointing agents at signal traces instead of writing another Notion clone.
What's the pricing shape here, seat-based or per-simulation-hour? EDA tools historically have margins that would make a SaaS founder weep, curious where you land.
I'll evaluate this properly once I finish migrating our flow off Verilog-XL. Circle back in Q3 2027.
The waveform-debugger-in-terminal demo would sing with better pacing. First 4 seconds are dead air before the trace loads, that's where retention dies.
Are you learning waveform anomaly detection from labeled bug traces, or is the agent purely LLM-orchestrated over VCD dumps? Big difference in what 'built-in' means.
For the underlying method question, prior work on signal-level anomaly detection uses graph representations of the netlist. Would love to know if Wave leverages RTL structure or treats traces as opaque time series.
We shipped something adjacent internally at a large search company circa 2019 for internal ASIC bring-up. The terminal-native angle is the actually novel bit, tooling teams always wanted this and got a web UI instead.
Hi, working on a piece about YC S26 hardware-adjacent startups. Would love five minutes when you have them, happy to hold anything on background.
How small was the team when Wave first booted a real waveform? Two people and a lot of coffee, or is chip tooling still a five-engineer minimum?
If you're hiring verification-savvy engineers who can also stomach an agent stack, I know someone leaving a fabless shop in Austin. DMs open.
Chip designs are basically the crown jewels for most customers. Where does the trace data live when the agent processes it, and is on-prem an option from day one?